Method for manufacturing semiconductor device

ABSTRACT

A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on the basis of the measurement value. After forming the encapsulation resin layer during the process of manufacturing the semiconductor device, the removal area is removed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation application of U.S. patentapplication Ser. No. 14/762,320, filed on Jul. 21, 2015, which is basedupon and claims the benefit of priority from Japanese patent applicationNo. 2013-009285, filed on Jan. 22, 2013, all of which are incorporatedherein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to the shape of a semiconductor device,and in particular the present invention relates to restricting anincreased profile height due to curvature caused by differences inthermal expansion coefficient among members forming a semiconductordevice.

BACKGROUND

BGA (Ball Grid Array) semiconductor devices are generally constructed insuch a way that a semiconductor chip is mounted on one surface of awiring board, and that surface of the wiring board is covered by asealing resin so that the semiconductor chip is covered, as described inPatent Document 1, for example.

The wiring board, semiconductor chip and sealing resin forming asemiconductor device normally have different thermal expansioncoefficients. Curvature is produced in the semiconductor device due tothe difference in thermal expansion coefficients. In a semiconductordevice in which convex curvature has been produced, the central partprojects from the surrounding part, whereas in a semiconductor device inwhich concave curvature has been produced, the surrounding part projectsfrom the central part. In either case, the actual semiconductor devicewhich has curved due to the difference in thermal expansion coefficientsof the constituent members has regions which project to a greater extentthan a semiconductor device in an ideal state without any curvature. Thepresence of these projections acts in a direction which increases theoverall height of the semiconductor device and is a factor insubstantially increasing the profile height of the semiconductor device.

There has been a demand for thinner and more compact portable devicesetc. in recent years, and the semiconductor devices incorporated in suchdevices also have to be thinner and more compact. Under thesecircumstances, if a large amount of curvature is produced in asemiconductor device, the overall height of the semiconductor deviceafter mounting increases and as a result a situation arises in which thesemiconductor device can no longer be incorporated into a portabledevice and the production yield deteriorates.

By making the thermal expansion coefficients of the constituent membersof the semiconductor device as close as possible to one another it ispossible to restrict the magnitude of curvature to a certain extent.However, there are limits to this and so there are constraints on thecombination of materials in semiconductor devices.

Patent Document 2 may be cited as a document describing an inventionassociated with the present invention. That document describes atechnique in which four locations at the corners of a semiconductordevice are endowed with a recessed shape in order to prevent crackingand chipping at the corners of the semiconductor device. That documentdoes not take account of curvature of the semiconductor device.Furthermore, a new step is added in that document in order to formrecesses in a sealing resin.

PATENT DOCUMENTS

Patent Documents 1 and 2 are cited as documents describing technologyrelating to the present invention.

Patent Document 1: JP 2012-169398 A

Patent Document 2: JP 2002-100702 A

SUMMARY OF THE INVENTION Problem to be Solved by the Invention

The present invention has been devised in view of the situationdescribed above, and the problem to be solved by the present inventionlies in preventing an increased profile height in a semiconductor deviceas a result of part of the semiconductor device projecting due to shapedistortion such as curvature produced in the semiconductor device.

Means for Solving the Problem

In order to solve the abovementioned problem, one mode of the presentinvention provides a method for manufacturing a semiconductor device,characterized in that it comprises the following stages: a samplemanufacturing stage in which a sample semiconductor device ismanufactured; a sample measurement stage in which a measurement valuerelating to curvature of the sample is taken; a removal regiondetermination stage in which a removal region constituting a region forremoval from a sealing resin layer covering one surface of thesemiconductor device positioned on the opposite side of a substrate whenthe semiconductor device is mounted on said substrate is determined inaccordance with the measurement value; and a manufacturing stage whichis a stage in which the semiconductor device is manufactured, comprisinga step in which the sealing resin layer is formed, after which theremoval region is removed.

Advantage of the Invention

According to the present invention, a removal region including a regionprojecting from a semiconductor device is determined and removed inaccordance with a measurement result of a sample semiconductor device,and therefore it is possible to prevent an increased profile height ofthe semiconductor device which would occur if a projecting region wereleft in place.

BRIEF DESCRIPTION OF THE FIGURES

[FIG. 1] is a flowchart for illustrating the method for manufacturing asemiconductor device according to the present invention;

[FIG. 2] is a diagram to illustrate a sample 1 curved into a concaveshape, which is manufactured prior to manufacture of the semiconductordevice serving as the final target article by the method formanufacturing a semiconductor device according to the present invention;

[FIG. 3] is a diagram to illustrate an example of a removal region 8;

[FIG. 4] is a diagram to illustrate an example of a removal region 8;

[FIG. 5] is a diagram to illustrate a sample 20 curved into a convexshape, which is manufactured prior to manufacture of the semiconductordevice serving as the final target article by the method formanufacturing a semiconductor device according to the present invention;

[FIG. 6] is a diagram to illustrate an example of a removal region 27;

[FIG. 7] is a diagram to illustrate an example of a removal region 27;

[FIG. 8] is a plan view showing the schematic configuration of asemiconductor device 40 according to Exemplary Embodiment 1;

[FIG. 9] is a view in cross section showing the schematic configurationbetween A-A′ in FIG. 8;

[FIG. 10] is a view in cross section showing the schematic configurationbetween B-B′ in FIG. 8;

[FIG. 11] is a view in cross section showing a structure in which thesemiconductor device 40 according to Exemplary Embodiment 1 is stackedas a package on another semiconductor device;

[FIG. 12] is a diagram to illustrate an example of the method formanufacturing the semiconductor device 40;

[FIG. 13] is a diagram of a wiring motherboard 70 in the step in FIG.12(a), seen looking down from above;

[FIG. 14] is a diagram of the wiring motherboard 70 in the step in FIG.12(b), seen looking down from above;

[FIG. 15] is a diagram of the wiring motherboard 70 in the step in FIG.12(e), seen looking down from above;

[FIG. 16] is a plan view showing the schematic configuration of asemiconductor device 80 according to Exemplary Embodiment 2;

[FIG. 17] is a view in cross section showing the schematic configurationbetween E-E′ in FIG. 16;

[FIG. 18] is a view in cross section showing the schematic configurationbetween F-F′ in FIG. 16;

[FIG. 19] is a plan view showing the schematic configuration of asemiconductor device 90 according to Exemplary Embodiment 3;

[FIG. 20] is a view in cross section showing the schematic configurationbetween G-G′ in FIG. 19;

[FIG. 21] is a view in cross section showing the schematic configurationbetween H-H′ in FIG. 19;

[FIG. 22] is a view in the cross section A-A′ of a semiconductor device100 according to Exemplary Embodiment 4; and

[FIG. 23] is a view in the cross section B-B′ of the semiconductordevice 100 according to Exemplary Embodiment 4.

MODE OF EMBODIMENT OF THE INVENTION

The method for manufacturing a semiconductor device according to a modeof embodiment of the present invention will be described. According tothe inventive manufacturing method, a sample of a semiconductor deviceis manufactured prior to the manufacture of the semiconductor deviceserving as the final target product, and the sample is measured in orderto acquire measurement values relating to the magnitude and direction ofcurvature. Curvature causes the surface of the sample semiconductordevice mounted on a substrate, to be more specific part of a sealingresin layer, to extend beyond a predetermined reference surface. If theregion beyond the reference surface is referred to as a “projectingregion”, then according to this method, a region including theprojecting region of the sealing resin layer is determined to be aremoval region which is removed in the process of manufacturing thesemiconductor device serving as the product.

Referring to FIG. 1, a sample semiconductor device is manufactured priorto the manufacture of the semiconductor device which is manufactured asthe final product (step S1). As shown in FIG. 2, a sample 1 comprises: awiring board 2, a semiconductor chip 3 which is mounted on the wiringboard 2, a sealing resin layer 4 for covering the wiring board 2 and thesemiconductor chip 3, a substrate 6 for mounting the wiring board 2, andsolder balls 5 for joining the wiring board 2 and the substrate 6. Themethod for manufacturing the sample 1 is the same as the method formanufacturing a conventional semiconductor device. The wiring board 2,semiconductor chip 3 and sealing resin layer 4 are made of differentmaterials, so the thermal expansion coefficients thereof are alsodifferent. Concave curvature is produced in the sample 1 on thesubstrate 6, as shown in FIG. 2, as a result of this difference inthermal expansion coefficient and of the size and shape etc. of thewiring board 2 semiconductor chip 3 and sealing resin layer 4. In FIG. 2the actual curvature of a semiconductor device has been exaggerated inorder to aid an understanding of the present invention.

The magnitude and direction etc. of the curvature and values relating tothe curvature are then measured by actually measuring the sample 1 (stepS2).

The projecting region is then obtained in accordance with themeasurement values acquired in step S2 and a predetermined referencesurface 7 (step S3). The reference surface 7 constitutes, for example,the height of the semiconductor device from the substrate surface when asemiconductor device constituting the final target article is mounted onthe substrate using the solder balls. When concave curvature is producedas with the sample 1, the peripheral edges of the sample 1, and inparticular the upper sides of the four corners of the sealing resinlayer 4 if the sample is rectangular, as shown in FIG. 3 and FIG. 4,form projecting regions 11 shaped like triangular pyramids.

Removal regions 8 are then determined in accordance with the projectingregions 11 (step S4). The shape of the removal regions 8 should includethe projecting regions 11. For example, the removal region 8 in FIG. 3serves to remove the projecting region 11 from the sealing resin layer 4as part of an imaginary cylinder in which the oblique line on the leftof the right-angled triangle indicating the projecting region 11 in FIG.3 constitutes the center axis, and the oblique line on the right of thesame right-angled triangle constitutes the radius. Furthermore, theremoval region 8 in FIG. 4 serves to remove the projecting region 11from the sealing resin layer 4 as part of an imaginary sphere having acenter on the line of extension of the oblique line on the left of theright-angled triangle indicating the projecting region 11 in FIG. 3.

After the removal regions 8 have been determined in this way, thesemiconductor device serving as the final product is manufactured. Theremoval regions 8 are removed in the manufacturing process (step S5).

The abovementioned description relates to a case in which thesemiconductor device is curved in a concave shape, but the presentinvention may equally be applied if the semiconductor device is curvedin a convex shape. As shown in FIG. 5, a sample 20 is curved in a convexshape. In the same way as with the sample 1, the sample 20 comprises awiring board 21, a semiconductor chip 22, a sealing resin layer 23,solder balls 24 and a substrate 25. The sample 20 follows a convexshape, so the center thereof is higher than a reference surface 26. Aremoval region 27 should have a shape that includes a projecting region31, and as shown in FIG. 6, the removal region 27 may serve to removepart of the sealing resin layer 23 in the shape of a cylinder includingthe projecting region 31, or as shown in FIG. 7, the removal region 27may serve to remove part of the sealing resin layer 23 as part of asphere including the projecting region 31, for example.

Exemplary Embodiment 1

The semiconductor device 40 shown in FIG. 8 will be described asExemplary Embodiment 1. The semiconductor device 40 is manufactured inaccordance with the abovementioned method for manufacturing asemiconductor device and corresponds to a sample 1 having concavecurvature. As shown in FIG. 8, when the semiconductor device 40 isviewed from above while mounted on a substrate which is not depicted,first recesses 42 a, 42 b, 42 c, 42 d are formed at the four corners ofthe surface of a sealing resin layer 41 covering the surface of thesemiconductor device 40 and correspond to the abovementioned removalregions 8. Furthermore, a second recess 43 constituting anidentification mark, such as a company name or product name (“XXX” isgiven as an example in the figure) is formed in a substantially centralposition of the sealing resin layer 41. The semiconductor device 40 ismounted on a substrate which is not depicted with the interposition ofsolder balls which are arranged at the positions of the circles drawn indotted lines in the figure.

As shown in the cross section A-A in FIG. 9 and the cross section B-B inFIG. 10, the semiconductor device 40 has a structure in which asemiconductor chip 46 bonded by an adhesive member 45 to a wiring board44 is covered by the sealing resin layer 41. The semiconductor chip 46is a memory chip, for example. Lands 48 arranged correspondingly withsolder balls 47 are provided on the lower surface of the wiring board44. The areas between electrode pads 49 of the semiconductor chip 46 andconnection pads 50 of the wiring board 44 are connected by wires 51.

As is clear from FIG. 9 and FIG. 10, the semiconductor device 40 hasconcave curvature. As shown in FIG. 10, the curvature on the diagonalsof the wiring board 44 in particular is larger than in the otherdirections, and the height is at a maximum at positions corresponding tothe four corners of the sealing resin layer 41. When there is concavecurvature as with the semiconductor device 40, the first recesses 42a-42 d are therefore formed at the four corners of the sealing resinlayer 41, and as a result it is possible to reduce the maximum height ofthe semiconductor device 40. The first recesses 42 a-42 d are formed toa greater depth than the second recess 43. For example, the firstrecesses 42 a-42 d are formed to a depth of 10-60 μm and the secondrecess 43 is formed to a depth of 5-30 μm.

According to Exemplary Embodiment 1, the semiconductor device 40 hasconcave curvature and the overall height of the semiconductor device canbe reduced by forming the first recesses 42 a-42 d at the highest pointson the surface of the sealing resin layer 41, so the overall heightafter mounting can also be reduced. Furthermore, the amount of curvaturecan be reduced by reducing the amount of resin at the corners of thesealing resin layer 41. In addition, when the semiconductor device 40 ismass produced, it is possible to restrict fluctuations in curvatureamong individual semiconductor devices 40. As a result, the incidence ofmounting defects when the semiconductor device 40 is incorporated intoanother device such as a portable information processor can be reducedand the assembly yield can be improved.

It should be noted that the second recess 43 is preferably formed on thesurface avoiding positions directly above the wires 51 connecting thesemiconductor chip 46 and the wiring board 44, as shown in FIG. 9. Byforming the second recess 43 in such a position, it is possible toprevent the wires 51 from becoming exposed from the sealing resin layer41 when the mark is formed by laser marking.

As shown in FIG. 11, the semiconductor device 40 may be stacked onanother semiconductor device 60. In the semiconductor device 60, the gapbetween a wiring board 61 and a semiconductor chip 62 is filled with anunderfill material 63. The semiconductor chip 62 is a logic chip, forexample, and the semiconductor chip 62 is flip-chip mounted on thewiring board 61. The electrode pads 64 of the semiconductor chip 62 andconnection pads 65 of the wiring board 61 are connected by way of bumps66. Connection lands 67 are provided on the upper surface of the wiringboard 61. The solder balls 47 are formed between the lands 48 of thesemiconductor device 40 and the connection lands 67 of the semiconductordevice 60. Lands 68 are further provided on the lower surface of thewiring board 61. The semiconductor device 60 (and the semiconductordevice 40 mounted thereon) are mounted on another wiring board which isnot depicted by forming solder balls 69 below the lands 68.

Unlike the semiconductor device 40, a sealing resin layer is not formedon the semiconductor device 60, so there is less curvature than with thesemiconductor device 40. As shown in FIG. 11, the semiconductor device40 having a large amount of curvature is mounted on the semiconductordevice 60 having a small amount of curvature. The diameter of the solderballs 47 is therefore preferably at least equal to the mounting heightof the semiconductor chip 62 when the semiconductor device 40 ismounted.

The method for manufacturing the semiconductor device 40 will bedescribed next with reference to FIG. 12.

A wiring motherboard 70 such as that shown in FIG. 12(a) is first of allprepared. In the following description, the upper surface refers to thesurface of the wiring motherboard 70 on the side on which thesemiconductor chips are mounted, while the lower surface refers to thesurface on the opposite side on which the solder balls are mounted. Thewiring motherboard 70 comprises a frame section 72 and product formationregions 71 corresponding to each individual semiconductor device. Dicinglines 73 are established between product formation regions 71 andbetween the product formation regions 71 and the frame section 72. Thelands 48 are formed on the lower surface of the wiring motherboard 70.FIG. 13 shows the upper surface of the wiring motherboard 70 at thispoint from above. The upper surface of the wiring motherboard 70 isdivided into 4×6 rectangular product formation regions 71 by means ofthe dicing lines 73. Connection pads 50 are formed in each of theproduct formation regions 71. Positioning holes 74 are provided in theframe section 72.

An adhesive member 45 is then applied to each of the product formationregions 71 and a semiconductor chip 46 is mounted thereon, as shown inFIG. 12(b). The electrode pads 49 and connection pads 50 are connectedby the wires 51 in each semiconductor chip. FIG. 14 shows the uppersurface of the wiring motherboard 70 at this point from above.

Next, as shown in FIG. 12(c), the upper surface side of the wiringmotherboard 70 is covered with a sealing resin layer 75 in which aheat-curable epoxy resin or the like has been pressurized and melted,and this layer is reacted and cured by means of heating or the like, asshown in FIG. 12(d).

The mark-forming step is carried out next. In the mark-forming step, thesurface of the sealing resin layer 75 is marked using a laser markingdevice, for example, as shown in FIG. 12(e), and the first recesses 42a-42 d and the second recess 43 are formed all together as a result.Hereafter, the first recesses 42 a-42 d will be referred to as the“first recesses 42” when there is no need to distinguish them.

A YVO4 (yttrium vanadium oxide) laser is used as the laser for the lasermarking device. The resin surface of the sealing resin layer 75 isirradiated with laser light and the resin surface is scraped away byaround 5-30 μm; as a result, the unevenness produced by the scrapingaway produces diffuse reflection and the mark can be identified by thecontrast with the molded resin surface. The required recess can beformed in the surface of the sealing resin layer 75 by irradiating thesealing resin layer 75 with laser light through a mask having apredetermined pattern, or by drawing a predetermined pattern on thesealing resin layer 75 using laser light.

As shown in FIG. 15, the first recesses 42 are formed as substantiallycircular recesses by means of laser marking at the positions ofintersection of the dicing lines 73 defining the product formationregions 71 on the wiring motherboard 70. The first recesses 42 aredeeper than the second recess 43 and are formed in such a way as to havedepth of the order of 10-60 μm, for example.

Furthermore, in the mark-forming step, an identification mark such as acompany name or product name etc. is formed as the second recess 43 ineach of the plurality of product formation regions 71 on the wiringmotherboard 70 at the same time as the first recesses 42 are formed. Thesecond recess 43 is formed by grinding the surface of the sealing resinlayer 41 of the individual semiconductor devices 40 by means of lasermarking. In view of this, the structure below the second recess 43 ispreferably taken into account for determining the position in which thesecond recess 43 is formed. For example, the second recess 43 ispreferably formed to avoid a position above the wires 51 on the surfaceof the sealing resin layer 41 in order to take account of the fact thatthe wiring board 44 and the semiconductor chip 46 are connected by wires51. By this means, the resin surface is ground by means of lasermarking, and as a result it is possible to avoid exposure of the wires51 from the surface of the sealing resin layer 41.

The solder balls 47 are then mounted on the lands 48 on the lowersurface of the wiring motherboard 70, as shown in FIG. 12(f).

Finally, in the substrate dicing step, as shown in FIG. 12(g), thesealing resin layer 75 is bonded to dicing tape, whereby the sealingresin layer 75 and the wiring motherboard 70 are supported by the dicingtape. After this, the wiring motherboard 70 and the sealing resin layer75 are cut vertically and horizontally along the dicing lines 73 using adicing blade in order to separate the structure into individual productformation regions 71, and individual semiconductor devices 40 areobtained as a result.

As shown in FIG. 8, an identification mark is formed as the secondrecess 43 in substantially the center of the surface of the sealingresin layer 41 of the semiconductor device 40 manufactured in this way,and arc-shaped recesses which are deeper than the second recess 43 andconstitute one quarter of a circumference are formed as the firstrecesses 42 at the four corners of the surface of the sealing resinlayer 41.

When concave curvature is produced—with the center of the semiconductordevice 40 being depressed and the surrounding part being raised forreasons including the difference in thermal expansion coefficient of thesealing resin layer 41, semiconductor chip 46 and wiring board44—curvature is produced in such a way that the four corners are thehighest when the semiconductor substrate 40 is mounted on a substrate orthe like, but the raised portions are ground as the first recesses 42,so it is possible to prevent the overall height of the semiconductordevice from increasing due to concave curvature.

Furthermore, the first recesses 42 are formed all together when thesecond recess 43 is formed in the mark-forming step. The second recess43, i.e. the identification mark, is formed in a step which is alsocarried out in the manufacture of a conventional semiconductor device.This means that there is no need to add a new step simply with the aimof forming the first recesses 42, and the first recesses 42 can beformed simply by modifying part of an existing step.

Exemplary Embodiment 2

A semiconductor device 80 constituting Exemplary Embodiment 2 of thepresent invention will be described. In Exemplary Embodiment 1 describedabove, cylindrical recesses having a quarter of an arc as the bottomsurface were formed as the first recesses 42 at the four corners of thesurface of the semiconductor device 40 having concave curvature. Thesemiconductor device 80 according to this exemplary embodiment likewisehas concave curvature and corresponds to the sample 1 in the mode ofembodiment, but the shape of the first recesses differs.

As shown in FIG. 16, the first recesses 82 in the semiconductor device80 are steps formed along the peripheral edge of a sealing resin layer81. The recesses 42 a-42 d are formed at the four corners of the sealingresin layer 81 in Exemplary Embodiment 1 and correspond to the removalregions 8 described in the mode of embodiment, but in ExemplaryEmbodiment 2, recesses are also formed in the straight line portions atthe outer periphery of the sealing resin layer 81 in addition to at thefour corners of the sealing resin layer 81. The second recess 43,semiconductor chip 46 and solder balls 47 etc. are the same as inExemplary Embodiment 1 and bear the same reference symbols, and theywill not be described again.

Here, a comparison of FIG. 9 pertaining to Exemplary Embodiment 1 andFIG. 17 pertaining to Exemplary Embodiment 2 will be described. InExemplary Embodiment 1, the first recesses 42 are formed only at thefour corners, so it is not possible to avoid an increase in the heightof the areas on the sides of the sealing resin layer 41 caused bycurvature in a direction parallel to the outer peripheral sides of thesemiconductor device 40, for example curvature in the direction A-A′ inFIG. 8. In contrast to this, in Exemplary Embodiment 2, steps are formedalong the outer peripheral sides of the semiconductor device 80, so itis possible to avoid an increase in the height of the areas on the sidesof the sealing resin layer 81 caused by curvature in the direction E-E′,namely saddle-shaped curvature.

In addition, as will be understood from a comparison of FIG. 10pertaining to Exemplary Embodiment 1 and FIG. 18 pertaining to ExemplaryEmbodiment 2, the semiconductor device 80 also has recesses at the fourcorners and is in this respect the same as the semiconductor device 40,so it is also possible to avoid an increased profile height with respectto curvature in the direction F-F′ in FIG. 16, namely curvature in thedirection of the diagonal of the semiconductor device 80, in the sameway as in Exemplary Embodiment 1.

It should be noted that the method for manufacturing the semiconductordevice 80 is substantially the same as the method for manufacturing asemiconductor device 40. In Exemplary Embodiment 1, the semiconductordevice 40 was manufactured by forming circular recesses at theintersections of the dicing lines 73, but in Exemplary Embodiment 2,strip-like recesses are formed along the dicing lines 73 and are notlimited to the intersections of the dicing lines 73.

Exemplary Embodiment 3

A semiconductor device 90 constituting Exemplary Embodiment 3 of thepresent invention will be described. Exemplary Embodiments 1 and 2 arebased on a semiconductor device having concave curvature. In contrast tothis, the semiconductor device 90 has convex curvature and correspondsto the sample 20 in the mode of embodiment. The height of the centralpart of a sealing resin layer 91 is relatively higher because of theconvex curvature and the height of the surrounding part is relativelylower.

As shown in FIG. 19, the semiconductor device 90 has first and secondrecesses in the same way as in Exemplary Embodiments 1 and 2, but thepositions of the recesses are different. A first recess 92 is formed insubstantially the center of the surface of the sealing resin layer 91 asa recess corresponding to the removal region 8 described in the mode ofembodiment. Furthermore, a second recess 93 representing anidentification mark or the like of the semiconductor device 90 is formedbetween an end of the semiconductor device 90 and the first recess 92 onthe surface of the sealing resin layer 91. Constituent elements whichare the same as in Exemplary Embodiments 1 and 2 bear the same referencesymbols and will not be described again. The first recess 92 ispreferably formed avoiding the area above the wires 51, as shown in FIG.20. This is to avoid exposure of the wires 51 from the first recess 92.

The height of the central portion of the sealing resin layer 91 is, byits nature, the greatest due to convex curvature of the sealing resinlayer 91, and as a result the height of the semiconductor device 90 ispushed upward; by forming the first recess 92, it is possible to avoidan increased profile height of the semiconductor device 90 caused byconvex curvature.

Exemplary Embodiment 4

In the mode of embodiment and the exemplary embodiments described above,a description was given of a semiconductor device having a structure inwhich a single semiconductor chip is mounted in a single productformation region and covered by a sealing resin layer, but the presentinvention may equally be applied to a semiconductor device having astructure in which a plurality of semiconductor chips are mounted in asingle product formation region and covered by a sealing resin layer. Asemiconductor device 100 having a structure in which two semiconductorchips are stacked and mounted in a single product formation region andcovered by a sealing resin layer will be described as ExemplaryEmbodiment 4.

Exemplary Embodiment 4 relates to an example in which the presentinvention is applied to a semiconductor device having concave curvaturein the same way as Exemplary Embodiment 1, but in Exemplary Embodiment1, a single semiconductor chip 46 is mounted on a wiring board 44,whereas in the semiconductor device 100 according to this exemplaryembodiment, an adhesive member 101 is applied to the semiconductor chip46 and a separate semiconductor chip 102 is further mounted thereon.

The appearance of the semiconductor device 100 when seen from above isno different than the semiconductor device 40 shown in FIG. 8. FIG. 22shows a cross section corresponding to the cross section A-A′ in FIG. 8,and FIG. 23 shows a cross section corresponding to the cross sectionB-B′. As is clear from FIG. 23 in particular, in this exemplaryembodiment, an increased profile height of the semiconductor device 100is prevented by forming the first recesses 42 a-42 d at the positionshaving the greatest height as a result of concave curvature producedalong the diagonal direction of the semiconductor device 100, i.e. atthe four corners of the surface of the sealing resin layer 41.

The invention devised by the present inventor has been described inaccordance with exemplary embodiments, but the present invention is notlimited to these exemplary embodiments and it goes without saying thatvarious modifications may be made within a scope that does not departfrom the essential point of the present invention.

For example, as examples of the removal regions 8 referred to in themode of embodiment, arc-shaped recesses having a center angle of 90° areformed at the four corners of a semiconductor device by forming circularrecesses at intersections of dicing lines and cutting along the dicinglines in a semiconductor device having concave curvature (ExemplaryEmbodiment 1), strip-like recesses are formed along the four sides of asemiconductor device in such a way as to surround the sides by formingstrip-like recesses along dicing lines and cutting along the dicinglines in a semiconductor device likewise having concave curvature(Exemplary Embodiment 2), and a circular recess is formed insubstantially the center of a semiconductor device having convexcurvature, but the present invention is not limited to these examples.According to one mode of the present invention, when curvature isproduced in a semiconductor device because of differences in the thermalexpansion coefficients or shapes etc. among the sealing resin layer,semiconductor chip and wiring board, a sample of the semiconductordevice is manufactured, the position where the height of the sample isgreatest due to curvature is identified, and a portion including thatposition is ground at the same time as an identification mark is ground,preferably using a laser marking device or the like, and as a result anincreased profile height of the semiconductor device which is the finalproduct is prevented. Accordingly, the position in which the firstrecesses corresponding to the removal regions are formed should includethe location or locations which actually have the highest profile whenthe sample is measured, and the present invention should not beconstrued as being limited to the shapes or positions described above.

Part or all of the mode of embodiment described above may also bedescribed as in the following additional notes, but the mode ofembodiment is not limited thereby.

(Additional Note 1)

A semiconductor device characterized in that it comprises:

a wiring board;

a semiconductor chip mounted on one surface of the wiring board; and

a sealing resin layer formed on said surface of the wiring board in sucha way as to cover the semiconductor chip, and

the sealing resin layer has a surface on the opposite side to the wiringboard and said surface is curved in a predetermined direction, and

a recess is formed in the region constituting the highest point of saidsurface which is curved in said predetermined direction.

(Additional Note 2)

The semiconductor device as described in Additional Note 1,characterized in that a surface of the sealing resin layer is curved ina concave manner, and

the recess is formed in the region of an end of said surface of thesealing resin layer.

(Additional Note 3)

The semiconductor device as described in Additional Note 1,characterized in that a surface of the sealing resin layer is curved ina convex manner, and

the recess is formed in a region substantially in the center of saidsurface of the sealing resin layer.

(Additional Note 4)

The semiconductor device as described in Additional Note 2,characterized in that the recess is formed as a single element along anouter edge of the surface of the sealing resin layer.

(Additional Note 5)

The semiconductor device as described in Additional Note 1,characterized in that a mark is formed on the surface of the sealingresin layer, said mark being formed at a position avoiding the recess.

(Additional Note 6)

The semiconductor device as described in Additional Note 5,characterized in that the wiring board and the semiconductor chip areelectrically connected by a plurality of wires, and

the recess and the mark are formed at positions avoiding a region on thesurface of the sealing resin layer positioned above the plurality ofwires.

(Additional Note 7)

A semiconductor device characterized in that it comprises:

a wiring board;

a semiconductor chip mounted on one surface of the wiring board;

a sealing resin layer formed on said surface of the wiring board in sucha way as to cover the semiconductor chip;

a first recess formed on a surface of the sealing resin layer; and

a second recess which is formed on a surface of the sealing resin layerand has a greater depth from the surface than the first recess.

(Additional Note 8)

The semiconductor device as described in Additional Note 7,characterized in that the first recess is formed in a regionsubstantially in the center of said surface of the sealing resin layer,and

the second recess is formed in the region of an end of said surface ofthe sealing resin layer.

(Additional Note 9)

The semiconductor device as described in Additional Note 7,characterized in that the second recess is formed in a regionsubstantially in the center of said surface of the sealing resin layer,and

the first recess is formed in a different region than the second recesson the surface of the sealing resin layer.

(Additional Note 10)

The semiconductor device as described in Additional Note 8,characterized in that the second recess is formed as a single elementalong an outer edge of the surface of the sealing resin layer.

(Additional Note 11)

The semiconductor device as described in Additional Note 7,characterized in that the first recess is a mark formed on said surfaceof the sealing resin layer.

(Additional Note 12)

The semiconductor device as described in Additional Note 7,characterized in that the wiring board and the semiconductor chip areelectrically connected by a plurality of wires, and

the first recess and the second recess are formed at positions avoidinga region on the surface of the sealing resin layer positioned above theplurality of wires.

It should be noted that this application claims the benefit of prioritybased on Japanese Patent Application 2013-9285 filed on Jan. 22, 2013,the disclosure of which is hereby incorporated in its entirety.

KEY TO SYMBOLS

1, 20 . . . Sample

2, 21 . . . Wiring board

3, 22, 62, 102 . . . Semiconductor chip

4, 23, 41, 75, 81, 91 . . . Sealing resin layer

5, 24 . . . Solder ball

6, 25 . . . Substrate

7, 26 . . . Reference surface

8, 27 . . . Removal region

11, 31 . . . Projecting region

12, 13, 32, 33 . . . Non-projecting region

40, 60, 80, 90, 100 . . . Semiconductor device

42 a, 42 b, 42 c, 42 d, 82, 93 . . . First recess

43, 92 . . . Second recess

44 . . . Wiring board

45, 101 . . . Adhesive member

46 . . . Semiconductor chip

47, 69 . . . Solder ball

48, 68 . . . Land

49, 64 . . . Electrode pad

50, 65 . . . Connection pad

51 . . . Wire

63 . . . Underfill

66 . . . Bump

67 . . . Connection land

70 . . . Wiring motherboard

71 . . . Product formation region

72 . . . Frame section

73 . . . Dicing line

74 . . . Positioning hole

What is claimed is:
 1. A method for manufacturing a semiconductor device, comprising: manufacturing a sample semiconductor device; taking a measurement value relating to curvature of the sample; determining a removal region having a region for removal from a sealing resin layer covering one surface of the semiconductor device positioned on the opposite side of a substrate when the semiconductor device is mounted on said substrate in accordance with the measurement value; forming the sealing resin layer; and removing the removal region. 